The HDLG is a self-contained in-line HD/SD SDI logo generator with the form and function of the existing LG1Plus/LG4 family of logo generators. The HDLG provides storage for up to four 512Hx512V pixel 24-bit static logos.
The HD/SD SDI program video path is a full 10-bit resolution, while the resolution of the logo is 8-bit RGB (24-bit total) bitmap image. These logos can be switched on/off or faded in/out of the program path using Windows based software interface, a real-time clock scheduler, an external GPI input or directly from the Front Panel. The transparency of the insert and the fade rate are also selectable.
The HDLG ships with a Windows based GUI that accommodates the loading and positioning of the image. Optional scheduling capabilities are available which make use of the internal time keeping capabilities of the HDLG on-board processor to run the schedule. The HDLG also accepts a one-pulse-per-second time-keeping pulse from an external source to maintain the timing accuracy of the on-board clock. The scheduler's database can then be stored in the HDLG and accessed by the GUI.
Although the HDLG has but one GPI input, its function is fully programmable. The GPI input could be used to over-ride the scheduler and display a pre-defined logo. For example, a logo indicating technical difficulties could be selected by the GPI input, regardless of the schedule. The GPI could also be programmed to cycle through the available logos, or just initiate the cut/fade in/out. It can be made level sensitive, as in - as long as it's activated, the default logo is displayed; or the logo cuts in when the GPI is high and cuts out when it's low. Or, it could be edge-sensitive, as in - each time the GPI is switched from low to high, the next logo in sequence is aired.
The input/output to the HDLG is serial digital (SDI) in either standard definition NTSC/PAL 480i/576i or the high-definition HDTV 720p50/60 and 1080i50/60 formats. The HDLG automatically detects the input standard and format without user intervention. The logo generator is intrinsically locked and formatted to the program channel input format. The latency between input and output of the HDLG is about 6 clock cycles, allowing it to be inserted in-line anywhere in the system. Additionally, because this device may be in-line and in a critical path, a failsafe bypass relay is included to route the SDI input directly to the output when power is lost or the unit is off.
PS-12/HC power supply (included): 120 VAC 60 Hz, 12 Vdc 1.5 A, UL Listed